Browse by Subject "high-level synthesis"
Now showing items 1-5 of 5
FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization (IEEE, 2009-01)While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. High level synthesis has been touted as a solution to ...
(ACM, 2009-01-17)Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, high-level binding algorithm for power and area reduction, ...
(2009-06-01)While technology scaling has presented many new and exciting opportunities, new design challenges have arisen. Smaller feature sizes have led to increased density and large variations in the delay and power characteristics ...
(2009-06-01)The move to deep submicron processes has brought about new problems that designers must contend with in order to obtain functional circuits. Process variation has been recognized as one of the leading issues that must be ...
(2015-05-01)With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy techniques with 2x and 3x area cost ...