Browse by Subject "low power"

  • Ko, Hyun Jae (2016-05)
    Nowadays, the main trend of designing a chip is to make it consume low power and occupy as small area as possible. Phase-locked Loop(PLL) is widely used in analog, digital, RF and communication systems. PLL is mostly used ...

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  • Mahalley, Makrand Bhagwat (2016-04-26)
    A reference clock generator is one of the most important components in many electronic devices. Common clock references are based on quartz crystals which offer high quality factor, good phase noise performance and excellent ...

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  • Crago, Neal (2012-09-18)
    This dissertation presents a novel decoupled latency tolerance technique for 1000-core data parallel processors. The approach focuses on developing instruction latency tolerance to improve performance for a single thread. ...

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  • Cromar, Scott A. (2009-06-01)
    While technology scaling has presented many new and exciting opportunities, new design challenges have arisen. Smaller feature sizes have led to increased density and large variations in the delay and power characteristics ...

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  • Kim, Eric P. (2010-01-06)
    Achieving energy-efficiency in nanoscale CMOS process technologies is made challenging due to the presence of process, temperature and voltage variations. In this thesis, we present soft N-modular redundancy (soft NMR) ...

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  • Abdallah, Rami (2012-06-27)
    Next-generation ubiquitous computing promises new levels in immersion and seamless technology integration enabled through a profusion of embedded signal processing (DSP)-heavy ultra-low-power (ULP) platforms. This ...

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  • Sun, Zelei (2016-04-28)
    High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose a method to generate clock-gating-friendly ...

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