Browse by Subject "power reduction"
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(ACM, 2009-01-17)Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, high-level binding algorithm for power and area reduction, ...
(2009-06-01)While technology scaling has presented many new and exciting opportunities, new design challenges have arisen. Smaller feature sizes have led to increased density and large variations in the delay and power characteristics ...