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Title:Architectural exploration of Si-IF many-die processors
Author(s):Petrisko, Daniel
Advisor(s):Kumar, Rakesh
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):Computer Architecture
Design Space Exploration
Waferscale
GPU
Si-IF
Abstract:Monolithic, single-die processors dominate today’s computing landscape. High performance systems achieve massive throughput by connecting large numbers of discrete chips – CPUs, GPUs, FPGAs – through high latency, low bandwidth interconnects. However, such systems provide limited performance scaling due to high communication costs between the discrete chips. This thesis proposes an alternate path for performance scaling: integrating many dies onto a single chip using a novel assembly technology – Silicon Interconnect Fabric (Si-IF). Many-die processors have both a technical and an economic advantage over their monolithic counterparts. We demonstrate potential benefits of a many-die approach using two approaches: efficient workload coverage design space exploration using many dies and evaluating a many-die wafer-scale GPU design.
Issue Date:2018-04-25
Type:Thesis
URI:http://hdl.handle.net/2142/101358
Rights Information:Copyright 2018 Daniel Petrisko
Date Available in IDEALS:2018-09-04
Date Deposited:2018-05


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