Files in this item

FilesDescriptionFormat

application/pdf

application/pdfNG-THESIS-2018.pdf (6MB)Restricted Access
(no description provided)PDF

Description

Title:An on-chip three-level boost converter for energy harvesting application
Author(s):Ng, Pei Han
Advisor(s):Pilawa-Podgurski, Robert
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):three-level boost converter
hybrid
switched capacitor (SC)
current mode control
delay-equalized
level shifter
capacitor balancing
Abstract:The first on-chip three-level boost converter with 0.28 mm2 die size is implemented using 65 nm CMOS technology. Leveraging the advantages of hybrid switched capacitor converters, the converter manages to provide a maximum output voltage of 4.5 V with the available 2.5 V devices in this technology. The issue of capacitor imbalance, which has always been one of the factors that hinder high-efficiency power converters, is resolved by the hybrid current mode controller proposed in this work. The hardware implementation demonstrates that the capacitor converges to its balance voltage within 270 μs. A new level shifter circuitry is established in this thesis to mitigate the effect of asymmetrical gate signals by the level shifter. This delay-equalized level shifter is able to produce a symmetric delay less than 1 ns, allowing high-frequency phase-shifted switching operation in a hybrid switched capacitor (SC) converter. Together with both output voltage regulation and capacitor balancing, the converter operates efficiently up to 45 MHz for wide input range from 0.5 V to 3.0 V. This converter achieves a peak efficiency of 97.5% and peak output current of 83 mA.
Issue Date:2018-07-19
Type:Thesis
URI:http://hdl.handle.net/2142/101831
Rights Information:Copyright 2018 Pei Han Ng
Date Available in IDEALS:2018-09-27
Date Deposited:2018-08


This item appears in the following Collection(s)

Item Statistics