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Description
Title: | MNA stamping for transient circuit simulation using SPICE |
Author(s): | Verma, Vishesh |
Advisor(s): | Schutt-Ainé, José E. |
Department / Program: | Electrical & Computer Eng |
Discipline: | Electrical & Computer Engr |
Degree Granting Institution: | University of Illinois at Urbana-Champaign |
Degree: | M.S. |
Genre: | Thesis |
Subject(s): | MNA
Stamping SPICE simulation |
Abstract: | Simulation is an essential step in the circuit design procedure, helping to verify the behavior of a designed circuit and dramatically reducing the time and effort required for debugging a given design. However, to analyze this behavior, we require an interface between the circuit design and the computer’s computational capabilities. This translation can be done in various ways depending on what aspect of the circuit is desired to be modeled (steady-state, transient, etc.). In this thesis, we explore two of these (steady-state MNA formulation and State-Space formulation) as a first step towards transient analysis. |
Issue Date: | 2018-12-03 |
Type: | Text |
URI: | http://hdl.handle.net/2142/102467 |
Rights Information: | Copyright 2018 Vishesh Verma |
Date Available in IDEALS: | 2019-02-06 |
Date Deposited: | 2018-12 |
This item appears in the following Collection(s)
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Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering -
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois