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Title:Timing Analysis of Digital VLSI Circuits with Emphasis on Interconnect Modeling, Delay, and Crosstalk
Author(s):Thong, Sidney
Subject(s):Interconnect
Crosstalk
VLSI circuits
Timing delay
Coupling
Issue Date:2000-05
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-00-2204, DAC-78
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103631
Sponsor:University of Illinois
Date Available in IDEALS:2019-05-02


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