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Title:Timing Analysisof Digital VLSI Circuits with Emphasis on Interconnect Modeling, Delay, and Crosstalk
Author(s):Thong, Sidney
Subject(s):interconnect
crosstalk
VLSI circuits
timing delay
coupling
Issue Date:2000
Publisher:Coordinated Science Laboratory. University of Illinois at Urbana-Champaign.
Series/Report:Coordinated Science Laboratory Report no.
Coordinated Science Laboratory Report no. UILU-ENG-00-2204, DAC-78
Genre:Report (Grant or Annual)
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103631
Sponsor:University of Illinois
Date Available in IDEALS:2019-05-02


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