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Title:A High Level Approach to Test Generation for VLSI Circuits
Author(s):Narain, Prakash
Subject(s):Test generation
VLSI circuits
Gate level
Circuit model
Algorithm
Issue Date:1992-03
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. CRHC-92-07
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103666
Sponsor:General Electric
Semiconductor Research Corp.
Date Available in IDEALS:2019-05-02


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