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Title:A High Level Approach to Test Generation for VLSI Circuits
Author(s):Narain, Prakash
Subject(s):test generation
VLSI circuits
gate level
circuit model
algorithm
Issue Date:1992
Publisher:Coordinated Science Laboratory. University of Illinois at Urbana-Champaign.
Series/Report:Coordinated Science Laboratory Report no.
Coordinated Science Laboratory Report, CRHC-92-07
Genre:Report (Grant or Annual)
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103666
Date Available in IDEALS:2019-05-02


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