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Title:Layout Generation for Deep Submicron CMOS Circuits
Author(s):Mansour, Makram M.
Subject(s):Systolic architecture
Detay models
Pcell
Parameterized cell
Automtic layout generation
Issue Date:2002
Publisher:Coordinated Science Laboratory. University of Illinois at Urbana-Champaign.
Series/Report:Coordinated Science Laboratory Report no.
Coordinated Science Laboratory Report no. UILU-ENG 02-2215, DAC-86
Genre:Report (Grant or Annual)
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103813
Sponsor:DARPA
Date Available in IDEALS:2019-05-10


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