Files in this item
Files | Description | Format |
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application/pdf ![]() ![]() | Full Text |
Description
Title: | Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests |
Author(s): | Sharma, Manish |
Subject(s): | VLSI testing
Delay fault testing Path delay test generation Design for test |
Issue Date: | 2003-10 |
Publisher: | Coordinated Science Laboratory, University of Illinois at Urbana-Champaign |
Series/Report: | Coordinated Science Laboratory Report no. UILU-ENG-03-2220, CRHC-03-11 |
Type: | Text |
Language: | English |
URI: | http://hdl.handle.net/2142/103854 |
Sponsor: | Semiconductor Research Corp. / SRC 99-TJ-717 DARPA Hewlett Packard |
Date Available in IDEALS: | 2019-05-17 |