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Title:VLSI Architectures for Iterative Channel Decoders
Author(s):Mansour, Mohammad M.
Subject(s):Turbo
LDPC
complexity
high-throughput
low-power
Issue Date:2003
Publisher:Coordinated Science Laboratory. University of Illinois at Urbana-Champaign.
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-03-2221, DAC 101
Genre:Report (Grant or Annual)
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103855
Sponsor:National Science Foundation
Date Available in IDEALS:2019-05-17


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