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Title:Study of Voltage and Process Variations Impact on the Path Delays of Arithmetic Units
Author(s):Kong, Chhay Tep
Subject(s):Voltage overscaling
Process variations
VOS error model
Arithmetic units
Adder architecture
Multiplier
MAC
FIR filter
error resilient DSP system
Issue Date:2008-11
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-08-2220, DAC-112
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103897
Sponsor:GSRC
Date Available in IDEALS:2019-05-20


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