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Title:Totally Self-checking Circuits and Testable CMOS Circuits
Author(s):Jha, Niraj Kumar
Subject(s):Concurrent error detection
CMOS
Domino-CMOS
Design
Encoding
Fault models
Self-checking circuits
Testability
nMOS
Issue Date:1986-06
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-86-2217, CSG-51
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103907
Sponsor:Office of Naval Research / N00039-80-C-0556
Semiconductor Research Corporation / SRC RSCH 84-06-049
Date Available in IDEALS:2019-05-21


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