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Title:Design of a 51.84-Mb/s Very High Speed Digital Subscriber Loop Reconfigurable Receiver Core
Author(s):Tschanz, James Willard
Subject(s):Digital subscriber loop
Adaptive equalizers
FIR digital filters
Dynamic reconfiguration
CMOS digital integrated circuits
ASIC design methodology
Issue Date:1999-09
Publisher:Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Series/Report:Coordinated Science Laboratory Report no. UILU-ENG-99-2227, DAC-76
Type:Text
Language:English
URI:http://hdl.handle.net/2142/103950
Sponsor:National Science Foundation / MIP 96-23737
Date Available in IDEALS:2019-05-23


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