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Title:Design and simulation of an analog delay locked loop with 180 nm technology
Author(s):Xia, Ruhao
Contributor(s):Hanumolu, Pavan Kumar
Subject(s):Delay Locked Loop
Phase Detector
Charge Pump
Voltage Controlled Delay Line
Abstract:This thesis describes designing an analog delayed locked loop, which will be used as part of an on-chip oscilloscope to generate the reference clock. Nowadays, people prefer on-chip measurement rather than common off-chip measurement, because as signal speed goes above several giga hertz, it is really hard to get very accurate results with off-chip measurement. Off-chip measurement will be influenced by the error and delay introduced when signal travels through package, PCB and connectors. Due to area consideration, on-chip oscilloscope is realized by using equivalent-time sampling, which needs DLL to generate sweeping delay. We will give the overview of architecture of a typical delay locked loop and give circuit description of different blocks of delay locked loop. Simulation results will be presented and analyzed.
Issue Date:2019-05
Genre:Other
Type:Text
Language:English
URI:http://hdl.handle.net/2142/104045
Date Available in IDEALS:2019-06-17


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