Files in this item

FilesDescriptionFormat

application/pdf

application/pdfRAJWARDAN-THESIS-2019.pdf (4MB)
(no description provided)PDF

Description

Title:Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology
Author(s):Rajwardan, Ashwarya
Advisor(s):Schutt-Ainé, José E.
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link
Abstract:This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.
Issue Date:2019-04-11
Type:Text
URI:http://hdl.handle.net/2142/104803
Rights Information:Copyright 2019 Ashwarya Rajwardan
Date Available in IDEALS:2019-08-23
Date Deposited:2019-05


This item appears in the following Collection(s)

Item Statistics