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Title:Dynamic power management for computing and communication
Author(s):Wei, Da
Director of Research:Hanumolu, Pavan Kumar; Schutt-Aine, Jose E.
Doctoral Committee Chair(s):Hanumolu, Pavan Kumar; Schutt-Aine, Jose E.
Doctoral Committee Member(s):Shanbhag, Naresh R.; Banerjee, Arijit
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):DC-DC converter
buck converter
fast transient response
advance notice
droop elimination
high switching frequency
high efficiency
Burst mode
rapid on/off
energy efficient
energy proportional
on-chip link
low power
power scalable
serial link
Multiplying delay locked loop (MDLL)
Abstract:Power management is essential in state-of-the-art many-core processor and system-on-chip designs due to the ever-increasing demand for performance and the diminishing benefits from technology scaling. With more and more integration of processing cores and functional blocks, aggressive power management is needed to keep the chips from overheating, to reduce the power requirement of the circuit boards and to allow data centers to host more machines within its power density limit. On the communication side, on- and off-chip total bandwidth has been increasing exponentially. However, the transceiver energy efficiency has by and large remained constant. Previous studies have explored the dynamic voltage and frequency scaling (DVFS) and Rapid on/off (ROO) techniques to optimize power efficiency of the transceivers for short-reach on-board chip to chip links. In this thesis, we explore power scaling techniques for on-chip high-speed links. To this end, A 10Gb/s rapid-on/off on-chip link transceiver is presented to demonstrate the architecture and circuit techniques to improve energy efficiency under all utilization levels. Fabricated in 65nm process, the proposed transceiver uses single-ended signaling with only 0.5\textmu m width and spacing and achieves 5Gb/m throughput density. Fast-lock signaling and clocking circuits greatly reduce the power-on time to 17ns. More than 125x effective data rate scaling (10Gb/s to 80Mb/s) is obtained with an energy efficiency degradation of only 1.6x (627fJ/b/mm to 997fJ/b/mm). When the supply voltage is scaled from 1V to 0.7V, the peak data rate scales from 10Gb/s to 6Gb/s and the power scalable range increases to 208x (10Gb/s to 48Mb/s) with energy efficiency degradation of only 1.2x (627fJ/b/mm to 753fJ/b/mm). On the computing side, more and more aggressive power management profiles are deployed on modern processors. However, their effectiveness is limited due to the potential supply droops caused by the large load current steps that compromises the power integrity. To mitigate the droops, we explore the circuit and architecture techniques for a fast load transient DC-DC converter that is able to withstand large load steps without a supply droop/overshoot. The proposed converter achieved 89% peak. It also achieved less than 8mV droop/overshoot when a 480mA/1ns load step is applied.
Issue Date:2019-07-08
Rights Information:Copyright 2019 Da Wei
Date Available in IDEALS:2019-11-26
Date Deposited:2019-08

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