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Title:Nanoscale electronic devices based on the hybrid stacks of two-dimensional materials and ferroelectric metal oxides
Author(s):Liu, Jialun
Director of Research:Zhu, Wenjuan
Doctoral Committee Chair(s):Lyding, Joseph W.
Doctoral Committee Member(s):Li, Xiuling; Cao, Qing
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):2D material, ferroelectrics
Abstract:Further scaling of complementary metal-oxide-semiconductor (CMOS) dimensions will soon lead to a tremendous rise in power consumption while limited gain in the performance of integrated circuits. “Beyond-CMOS” devices, based on two-dimensional (2D) materials, can potentially overcome these limitations and further improve the performance, reduce energy consumption, and add novel functionalities to the CMOS platform. In this Ph.D. dissertation, we investigated energy efficient electronic devices based on a new hybrid material platform consisting of two-dimensional materials and ferroelectric metal oxides. The ferroelectric metal oxides provide programmable and non-volatile doping in the 2D materials, while the atomically thin body in 2D materials enables strong electrostatic control over the channel by the polarized ferroelectric metal oxides. We design and demonstrate a new type of classifier using ferroelectric graphene transistors, which can perform the “comparison” function in the analog domain instead of the traditional digital domain. This new type of classifier utilizes the ambipolar transport and zero bandgap of the graphene to perform the absolute difference function, |A-B|, directly. Unlike the image classifier based on silicon CMOS, the classifier based on ferroelectric graphene transistors only needs ONE transistor per pixel, which will significantly reduce chip area and energy consumption. More importantly, the embedded ferroelectric layer in the graphene transistor enables the non-volatile storage of the target image inside the analog device. Therefore, a single graphene transistor can perform both image storage and comparison functions concurrently. This in-memory computing will eliminate the need for frequent image loading/unloading, which will further reduce the power consumption related to the data transfer. We also explored non-volatile reconfigurable devices based on the hybrid stacks of ferroelectric materials and 2D materials. In traditional silicon CMOS, once the device is fabricated, its function is fixed as either an n-type or a p-type transistor. In this work, we show that functionality of this new type of device can be dynamically reconfigured during operation and the reconfiguration is non-volatile and reprogrammable. We have successfully demonstrated the electrostatic controlled reconfigurable devices based on black phosphorus and non-volatile reconfigurable devices based on molybdenum telluride and ferroelectric hafnium zirconium oxides. These reconfigurable devices will enable the logic circuits to evolve their functions on-demand. The 3D monolithic integration of these reconfigurable devices/circuits and memory blocks will enable in-memory computing and reduce the energy consumption and latency related to the transportation of “Big Data”. This work will open a new path toward the design of novel nano-function circuits based on unique material properties that are absent in traditional circuits based on CMOS logic transistors and Von Neumann architectures. These new devices will also enable a new computing paradigm, where the process latency and energy consumption will no longer be limited by the memory bottleneck.
Issue Date:2020-02-17
Type:Thesis
URI:http://hdl.handle.net/2142/107844
Rights Information:Copyright 2020 Jialun Liu
Date Available in IDEALS:2020-08-26
Date Deposited:2020-05


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