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Title:Ring oscillators for high performance clock synthesis and sensor interfaces
Author(s):Khashaba, Amr Tarek Ahmed Abdelrazik
Director of Research:Hanumolu, Pavan Kumar
Doctoral Committee Chair(s):Hanumolu, Pavan Kumar
Doctoral Committee Member(s):Shanbhag, Naresh; Schutt-Aine, Jose; Zhou, Jin
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Ring oscillator, multiphase generation, PLL, FLL, temperature sensor, temperature compensated oscillator
Abstract:Thanks to their small area and multiphase output, ring oscillators (ROs) play important roles in many systems. In this thesis, we study, analyze and propose novel solutions for RO-based applications. We cover three applications for ROs, namely, wireline clock generation, temperature-compensated references, and sensor interfaces. We start by focusing on RO-based clock generation where the phase noise is degraded due to jitter accumulation. We present a synthesizer architecture that uses a low-noise passive multiphase generator which does not suffer from jitter accumulation and digital background calibration to correct for errors in the multiphase generator. The synthesizer uses a standard 54MHz crystal to synthesize a 245fsrms 5GHz output while consuming only 8.2mW. For the frequency reference part, we propose a novel temperature-compensated oscillator (TCO) using a RO locked to RC reference using a frequency locked loop (FLL). High-resolution generated sequences are used to clock switched resistors of opposite temperature coefficients which serve as a reference resistor for the FLL. This results in excellent temperature coefficient of 8.4ppm/◦C from −40◦C to 85◦C while relying on only 2-point trim operation. The TCO also achieves a supply sensitivity of 80ppm/V and power efficiency of 1μW/MHz. For using the RO as a sensor interface, we propose a RO-based temperature sensor where the output period of the RO is locked to an RC sensor using a FLL. We propose a voltage mode FLL structure which guarantees very small area and low noise thanks to a novel 3-phase frequency-to-voltage converter which eliminates charge pump noise. The quantization noise is rejected by passing the 10 phases of the RO to an edge combiner. This allows building a compact temperature sensor occupying 8800μm2 area and achieving ±0.5◦C peak to peak inaccuracy after 1-point trim and 92fJ·K2 resolution FoM.
Issue Date:2020-04-29
Rights Information:Copyright 2020 Amr Khashaba
Date Available in IDEALS:2020-08-26
Date Deposited:2020-05

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