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Title:Circuits for time-domain signal processing
Author(s):Elmallah, Ahmed Safwat Mohamed Aboelenein
Director of Research:Hanumolu, Pavan Kumar
Doctoral Committee Chair(s):Hanumolu, Pavan Kumar
Doctoral Committee Member(s):Rosenbaum, Elyse; Schutt-Aine, Jose E.; Dragic, Peter D.
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Noise cancellation
Frequency synthesizer
Phase-locked loop
Delay-locked loop
Time to digital converter
Abstract:Advances in CMOS technologies have brought benefits to both digital and analog integrated circuits. However, lower output impedance, and reduced supply voltage have also brought new challenges especially to the design of analog circuits that typically operate in voltage/current domains. In this dissertation, circuits for processing the signal in the time-domain are explored where faster MOS transistors with improved timing accuracy are used to implement high precision scalable analog functions with lower power consumption. First, a wide dynamic range highly linear digital-to-time converter (DTC) using a two-step architecture is presented. The first stage is implemented using a counter while the second stage uses a high resolution digitally controlled delay line (DCDL). Background calibration is used to correct interstage gain errors and sequential switching is used to reduce DCDL non-linearity. Fabricated in 65nm CMOS process, the prototype DTC achieves 1.65ps peak integral non-linearity (INL) while consuming 10.13mW at 100MHz carrier frequency. The achieved range and resolution are 5.31ns and 330fs, respectively, while the integrated jitter is only 0.34ps rms. This translates to the best reported dynamic range of 70.2dB and a FoM of 31.1fJ/conv with 15dB improvement in dynamic range compared to state-of-the-art DTCs and more than 30% improvement in efficiency compared to DTCs on the same technology node. Second, a two-step counter/SAR time-to-digital converter (TDC) architecture is introduced to implement a power efficient high resolution high dynamic range TDC. Background calibration is proposed to solve circuit non-idealities that degrade TDC performance. Simulation results shows an effective number of bits (ENOB) of 13.4bits. Following that, a ring-VCO-based integer-N clock multiplier with feedforward noise cancellation is introduced to overcome the bandwidth limitation of conventional integer-N phase-locked loops (PLLs) by canceling the voltage controlled oscillator (VCO) noise in an open-loop fashion. Background calibration is presented to find the optimum gain for the noise cancellation path. Simulated in a 65nm CMOS process, the prototype NC-PLL achieves 300fs integrated noise over 100MHz bandwidth while reducing the consumed power to 6mW. A FoM of -242dB is achieved. Finally, a ring-VCO-based fractional-N clock multiplier with optimum threshold TDC (OT-TDC) and two-step quantization noise cancellation is proposed. The proposed PLL allows optimizing the noise performance by increasing the loop bandwidth to filter out the VCO noise while the TDC noise is optimized by calibrating the thresholds to match the output noise standard deviation, and the sigma-delta noise is canceled by using a two-step DTC in the feedback. To further improve the spurious performance, a piecewise linear (PWL) non-linearity calibration in performed to cancel the systematic non-linearity of the coarse DTC. Fabricated in a 65nm CMOS process, the prototype achieves a 405fs integrated noise over 30MHz bandwidth while consuming 11.7mW of power. The synthesizer achieves a worst-case fractional spur of -51dBc. The PWL non-linearity calibration improves the non-linearity spur by 12-14dB. The DPLL achieves a figure of merit of -237.2dB which is the best reported among state-of-the-art DPLLs.
Issue Date:2020-05-01
Rights Information:© 2020 Ahmed Elmallah
Date Available in IDEALS:2020-08-27
Date Deposited:2020-05

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