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Title:Network-on-chip design for a chiplet-based waferscale processor
Author(s):Cebry, Nicholas
Advisor(s):Kumar, Rakesh
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):network-on-chip
waferscale
Abstract:Motivated by the failing of Moore’s law and Dennard scaling, as well as increasingly large parallel tasks like machine learning and big data analysis, processors continue to increase in area and incorporate more computational cores. This growth requires innovation in manufacturing processes to build larger systems, and architectural changes to enable performance to scale acceptably. One significant architectural change is the shift from bus and crossbar based processor interconnections to networks-on-chip (NoCs). This thesis details the design of an NoC to enable a shared memory architecture in a chiplet-based wafer scale processor with architectural support for up to 14,336 cores.
Issue Date:2020-06-29
Type:Thesis
URI:http://hdl.handle.net/2142/108436
Rights Information:Copyright 2020 Nicholas Cebry
Date Available in IDEALS:2020-10-07
Date Deposited:2020-08


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