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Title:Dynamic amplifiers for analog-to-digital converters
Author(s):Nandi, Timir
Director of Research:Hanumolu, Pavan Kumar
Doctoral Committee Chair(s):Hanumolu, Pavan Kumar
Doctoral Committee Member(s):Banerjee, Arijit; Schutt-Aine, Jose E; Zhou, Jin
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):dynamic amplifier
reset gain
regeneration time
flash ADC
Abstract:Advances in CMOS technologies have brought benefits to both digital and analog integrated circuits. However, lower output impedance and reduced supply voltage have also caused newer challenges, especially for the design of operational amplifiers (op-amps) to implement gain. In this dissertation, dynamic/latch-based/regenerative amplifiers are explored where interrupted regeneration is used to implement the gain function. First, a 6-b current-domain interpolating pipelined flash analog-to-digital converter (ADC) is presented, where a novel current-shape-amplifier (CSA) based on a simple dynamic latch stage with interrupted regeneration is used to achieve 16 X interpolation factor using four interpolating stages. Thanks to this larger interpolation factor, ADC input capacitance is greatly reduced, which significantly eases the design of ADC driver circuits. The reduction in ADC throughput that accompanies classical interpolation methods is overcome by pipelining the proposed CSA-based interpolating stages. Fabricated in a 65 nm CMOS process, the prototype ADC consumes 43.8 mW at 1/1.25 V supply and achieves 26.8 dB signal-to-noise and distortion ratio (SNDR) and 35.2 dB spurious-free dynamic range (SFDR) at 4 GS/s with a 2 GHz input. Second, a study is conducted and a fully digital technique is proposed to calibrate the offset of interpolating flash ADCs. Compared to the state-of-the-art, this technique requires fewer comparators and needs fewer sets of input differential pairs. Offset cancellation is achieved by switching references (only during calibration) without extra loading at the input or the clock generator circuitry. The efficacy of this technique is demonstrated by simulating a 4 bit interpolating flash ADC which shows an effective number of bits (ENOB) improvement of 1.5 bits. Third, the non-idealities of the ADC are described and calibration techniques are proposed to improve the performance.
Issue Date:2020-05-18
Rights Information:© 2020 Timir Nandi
Date Available in IDEALS:2020-10-07
Date Deposited:2020-08

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