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Title:A study of worst-case integrated circuit optimization using iEDISON3.0
Author(s):Bieker, John Joseph
Advisor(s):Kang, Sung-Mo
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S. (master's)
Genre:Thesis
Subject(s):Circuit optimization
Issue Date:1994
Genre:Dissertation / Thesis
Type:Text
Language:English
URI:http://hdl.handle.net/2142/108870
Date Available in IDEALS:2020-10-22


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