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Title:Modeling Microarchitectural Side Channel Attacks for Fun & Profit
Author(s):Ravichandran, Joseph
Contributor(s):Fletcher, Chris
Degree:B.S. (bachelor's)
Genre:Thesis
Subject(s):microarchitectural attacks
interconnects
secure processors
Abstract:The discovery of hardware vulnerabilities has increasingly become more frequent in recent years. In the wake of the Spectre and Meltdown attacks, architectural security research has exposed many flaws in the processors we use every day that we trust to be secure. The purpose of this research is to construct a detailed architectural simulator for understanding, analyzing, and prototyping attacks in multicore computer systems. This work presents a custom multicore RISC-V computer system, complete with a custom multitasking kernel and simulation/ RTL verification environment. All of the hardware— each individual processor core, the memory and cache hierarchies, and the ring interconnect were designed with the intention of their use in analyzing real-world architectural attacks. This system allows for deep introspection into the state of the processor system, allowing for a complete understanding of the exact mechanisms of architectural attacks. The computer system implements an interconnect and cache model similar to those of real-world systems, allowing recent real-world attacks to be modeled. The simulation environment provides an array of tools that provide real-time deep introspection into the architectural state of the processor, allowing the user to have a complete picture of the attack being modeled at a glance. The simulator also provides GDB debugging support directly to the core, allowing the user to debug their attack software running on the simulated processor in real time.
Issue Date:2021-05
Genre:Dissertation / Thesis
Type:Text
Language:English
URI:http://hdl.handle.net/2142/110288
Date Available in IDEALS:2021-08-11


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