FPGA-based SSD Emulation

Abstract

Recent applications are demanding for more memory capacity. Researchers are seeking for other memory technologies such as NAND-flash enclosed an SSD to expand main-memory capacity. Researchers usually perform research on SSDs with (1) full system simulator, which is slow, (2) partial simulation, which is not accurate enough, and (3) real SSDs -- which are expensive and limited to a fixed design. Therefore, we design an FPGA based SSD emulator to find the relationship between SSD microarchitecture and system-wide performance. We run simulations to obtain time delay with different SSD microarchitecture -- number of channels, number of planes per channel and page size. Comparing the results we find that Increasing the channel number and planes per channel improves both random and sequential reading performance and increasing the page size only helps the sequential reads.