Area-constrained frequency estimation for focal plane arrays

Abstract

This thesis focuses on the problem of detecting the frequency and amplitude of signals generated by focal plane array (FPA) on a per-pixel basis, i.e., pixel-matched processing. Addressing this problem requires the design of signal processing algorithms and circuit architectures subject to stringent area constraints imposed by the pixel pitch, e.g., 144um2. Imaging systems incorporating FPAs with such pixel-matched processors will be able to perform real-time, energy-efficient and low-latency feature extraction in a massively parallel manner.

Classical approaches to sinusoidal frequency estimation and detection such as those based on the Discrete Fourier Transform (DFT) and its complexity-reduced version, the Fast Fourier Transform (FFT), are unsuitable for this application their use of complex-valued coefficients/weights.

In this thesis, we study the detection performance of the Discrete Hartley Transform (DHT) in addition to its variants which employ real-valued weights, as possible alternatives to the DFT. Our analysis indicates that thresholding the block averaged squared magnitude of the DHT samples generates a detection accuracy close to that of the DFT. However, the DHT suffers from the singularity problem (detection failure) when the frequency of the input is perfectly aligned with one of the frequency bins.

To solve the singularity problem, we propose two variants of the DHT: the Dithered Discrete Hartley Transform (D-DHT) and the Jittered Discrete Hartley Transform (J-DHT). Both variants solve the singularity problem by spreading the input signal energy across the signal spectrum. However, due to its narrower spreading effect, the D-DHT requires 2x fewer computations than the J-DHT to match the detection accuracy of the DFT.

Employing fixed-point analysis, we determine the minimum precision requirements for the D-DHT and the DFT when mapped to the direct dot-product (DP) architecture. The minimum precision values for the input, weight, and the accumulator is combined with the area estimates of a 1-bit full adder (FA) and a 1-bit register in a 65 nm CMOS process to obtain the area costs of the D-DHT and the DFT. Results show that the D-DHT achieves ~2x area reduction over the DFT with no significant impact on detection accuracy.

However, D-DHT's area is still ~3x greater than the pixel pitch. Since the FPA sampling rates are at least an order-of-magnitude lower than the maximum throughput achievable by a multiply-accumulate (MAC) unit in 65 nm CMOS process, our study suggests the use of bit-serial time-multiplexed K-pixel D-DHT architecture as a reasonable solution.