Files in this item



application/pdfSHAH-THESIS-2021.pdf (4MB)Restricted to U of Illinois
(no description provided)PDF


Title:High-voltage ESD PNP clamp simulation and design
Author(s):Shah, Milan
Advisor(s):Rosenbaum, Elyse
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):HV ESD
ESD Protection Devices
Abstract:In this work high-voltage Electrostatic discharge (ESD) PNPs are studied through TCAD simulation and device measurement. PNPs for three different voltage classes, 16 V, 65 V, and 100 V, in a 0.5-µm Bipolar CMOS DMOS (BCD) technology are used as the context for the study. The PNPs are varied in choices of topology, layout parameters, and connection configuration to determine how to design an optimal ESD PNP. Analysis of an unexpected two-part on-resistance is discussed. A detailed setup for running TCAD simulations for ESD devices that operate in breakdown, such as the ESD PNP, is also presented. The choice of model selection, differences between 2-D and 3-D simulation, and techniques for proper transmission line pulse (TLP) simulation are discussed. Careful considerations are made to account for the inaccuracies of the simulated doping profiles.
Issue Date:2021-01-11
Rights Information:Copyright 2021 Milan Shah
Date Available in IDEALS:2021-09-17
Date Deposited:2021-05

This item appears in the following Collection(s)

Item Statistics