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Title:Reconfigurable and heterogeneous architectures for efficient computing
Author(s):Dhar, Ashutosh
Director of Research:Chen, Deming
Doctoral Committee Chair(s):Chen, Deming
Doctoral Committee Member(s):Hwu, Wen-mei; Torrellas, Josep; Xiong, Jinjun; Huang, Jian
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Computer Architecture
Reconfigurable Computing
Abstract:The saturation of single-thread performance, along with the advent of the power wall, has resulted in the need for efficient use of area and power budgets. With the end of Dennard scaling, and the slow down of Moore's law, scaling from one process node to another no longer delivers gains in performance or power for general-purpose computing. Thus, there is an increase in the adoption of specialized hardware, tuned to the requirements of the application or domain. These accelerators promise high performance and energy efficiency. However, with the increasing complexity and resource requirements of applications and algorithms, there is also a need for more flexibility in these accelerator platforms. Along with high performance and energy efficiency, they must be able to cope with changes at an application and algorithmic level. In the face of these challenges, this dissertation explores the use of reconfiguration to balance flexibility, performance, and energy efficiency. We begin by presenting three novel approaches that explore the use of reconfiguration in the three dominant computing devices -- CPUs, GPUs, and FPGAs. First, we consider general-purpose GPU (GPGPU) computing and highlight the inefficiencies in GPGPU, and identify opportunities to leverage reconfiguration to address these inefficiencies. Our solution is novel reconfigurable GPU architecture that can adapt to the needs of GPUs by dynamically allocating computational and memory resources among GPU cores (SMs). Second, we consider the limitations of dynamic partial reconfiguration (DPR) in modern FPGAs. We observe that while DPR is a potentially powerful technique, it is difficult to leverage. Thus, we propose an end-to-end methodology to leverage dynamic partial reconfiguration in FPGAs. The approach scales from edge to cloud devices, and presents an overlay architecture and an integer linear programming (ILP) based scheduler and mapper. We also demonstrate the ability to simultaneously map multiple applications to one FPGA, and explore different scheduling and sharing strategies. Third, we attempt to bridge the gap between the efficiency of reconfigurable computing and near-memory computing for general-purpose computing. Thus, we consider a modern multi-core CPU, and propose a novel architecture that uses SRAM arrays in the last level cache to create a reconfigurable computing fabric. Our approach is cheap, fast, energy-efficient, non-invasive, and flexible. Finally, this dissertation concludes by considering the lessons learned from exploiting reconfiguration on CPUs, GPUs, and FPGAs, and asks how a modern reconfigurable computing device should be designed. With the explosion of data, large computational workloads, and increasing demands of efficiency, we propose a new memory-centric reconfigurable architecture, capable of fast dynamic reconfiguration and altering its compute to memory ratio and organization. We demonstrate significantly higher performance, density, and memory capacity than modern FPGAs.
Issue Date:2021-04-23
Rights Information:Copyright 2021 Ashutosh Dhar
Date Available in IDEALS:2021-09-17
Date Deposited:2021-05

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