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Title:Receivers for energy efficient optical interconnects
Author(s):Ahmed, Mostafa Gamal
Director of Research:Hanumolu, Pavan Kumar
Doctoral Committee Chair(s):Hanumolu, Pavan Kumar
Doctoral Committee Member(s):Dallesasse, John; Dragic, Peter D; Zhou, Jin
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):IM-DD optical links, Coherent optical links, optical receivers, Transimpedance amplifier, Decision feedback equalizer, Duobinary signaling, Automatic gain control, NRZ, PAM4, QPSK, 16QAM
Abstract:The recent exponential increase in internet traffic has created the need for more powerful data centers in which thousands of servers are connected with high bandwidth interconnects. Optical interconnects are increasingly deployed within the data centers to meet the growing bandwidth requirements. Both intensity modulation direct detection (IM-DD) optical links and coherent optical links are employed. The development of the optical interconnects is performed under tight power constraints due to inherent cooling limitations. Therefore, there has been a renewed focus on increasing data rates and improving the power efficiency of optical links. Among all IM-DD link components, laser diodes typically consume the most power. Their power dissipation is dictated by transmitting the amount of the optical power that meets the bit-error rate (BER) requirements under given channel loss and receiver sensitivity conditions. Consequently, improving IM-DD receiver sensitivity directly helps to lower laser diode power consumption. An inevitable trade-off between IM-DD receiver noise and bandwidth limits the maximum achievable receiver sensitivity at a given data rate and process technology. In this dissertation, design techniques to implement such high-sensitivity IM-DD optical receivers are presented. In the first technique, a high-sensitivity optical receiver is implemented using a combination of a low bandwidth transimpedance amplifier (TIA) and a 4-tap decision feedback equalizer (DFE) to overcome the noise-bandwidth trade-off. Fabricated in a 65nm CMOS technology and heterogeneously integrated with a photonic IC, the proposed optical receiver achieves OMA sensitivity of -16.8 dBm with 1.9 pJ/bit energy efficiency at 12 Gb/s. The second technique demonstrates a low-power high-sensitivity non-return-to-zero (NRZ) optical receiver using a combination of a limited bandwidth TIA and duobinary sampling to improve receiver sensitivity at high data rates. Duobinary sampling leverages the well-controlled TIA ISI to recover the transmitted data, making it much more hardware efficient than canceling the ISI using a DFE. Fabricated in a 65-nm CMOS process, the prototype receiver achieves optical modulation amplitude (OMA) sensitivity of -11.7 dBm at 16 Gb/s with 0.7 pJ/bit efficiency which represents more than 2.7x energy efficiency reduction and 30% data rate enhancement compared to the first technique. A comparison study is performed between NRZ, duobinary sampling, and PAM4 modulation formats, for IM-DD optical receivers for highest data rate operation with maximum receiver sensitivity. Both analysis and experimental results show that duobinary sampling achieves the highest receiver sensitivity compared to NRZ and PAM4 when operated with AFE bandwidth to data rate ratio smaller than 35% and allows for data rate operation as high as 4x the AFE bandwidth with 3 dB sensitivity penalty compared to 2x the AFE bandwidth in the NRZ case. On the other hand, high spectral efficiency offered by coherent optical communication links makes them attractive for the next generation 100-200 Gb/s data centers optical interconnects. Using advanced modulation schemes such as dual-polarization quadrature-amplitude modulation (DP-QAM) data rates beyond 200 Gb/s can be achieved. A key component of such links is the wide-bandwidth, high-linearity, and low-noise coherent optical receiver. In this dissertation, a fully differential coherent optical receiver architecture is presented in which a dual-feedback automatic gain control (AGC) loop is employed. The dual-feedback AGC loop controls a front-end variable-gain transimpedance amplifier (VG-TIA) and a variable-gain amplifier (VGA) to achieve both low-noise and high-linearity operation. A prototype dual TIA chip is fabricated in a 0.13-um SiGe BiCMOS process. The presented TIA achieves 20 pA/sqrt(Hz) input referred noise density, 27 GHz 3-dB bandwidth, and 1.5% total harmonic distortion at 1 mApp input photodiode current and 500 mVpp output voltage swing. This enables 34 Gbaud operation with bit error rate of 1E-10 and 5.4E-4 using DP-QPSK and DP-16QAM modulation formats at optical signal-to-noise ratios of 25 dB and 30 dB, respectively, demonstrating 100 Gb/s and 200 Gb/s single wavelength optical coherent receiver operation.
Issue Date:2021-03-01
Rights Information:Copyright 2021 Mostafa Ahmed
Date Available in IDEALS:2021-09-17
Date Deposited:2021-05

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