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Title:High-performance gallium nitride power devices with efficient edge termination structures compliant with plasma-assisted molecular-beam epitaxy based silicon nitride shadowed selective-area growth technique
Author(s):Sarker, Palash
Director of Research:Kim, Kyekyoon
Doctoral Committee Chair(s):Kim, Kyekyoon
Doctoral Committee Member(s):Hanumolu, Pavan K.; Rosenbaum, Elyse; Schutt-Aine, Jose E.
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):conductivity modulation (CM)
critical electric field
dielectric vertical sidewall appended edge termination (DiVSET)
edge termination (ET)
figure-of-merit (FOM)
inductively-coupled plasma reactive-ion etching (ICP-RIE)
junction barrier controlled Schottky (JBS)
merged p-i-n junction barrier controlled Schottky (MPJ)
merged p-i-n Schottky (MPS)
mixed-conduction diode
parallel-plane breakdown
non-punchthrouh (NPT)
punchthrough (PT)
reduced surface field (RESURF)
reverse recovery (RR)
reverse blocking efficiency
selective-area processing (SAP)
silicon nitride shadowed selective-area growth (SNS-SAG)
space-modulated junction termination extension (SM-JTE)
specific on-resistance
surface charge
technology computer-aided design (TCAD).
Abstract:The objective of this research is the design and development of ultra-low-leakage mixed-conduction gallium nitride (GaN) diodes with reverse blocking voltage approaching parallel-plane behavior. Although GaN is a promising wide bandgap (WBG) material, experimentally reported GaN power devices result in large leakage currents with lower reverse blocking efficiency. Two major de ciencies result in crippling underperformance in GaN power devices. First, conventional GaN processing methodologies, such as, ion-implantation and inductively-coupled plasma reactive-ion etching (ICP-RIE) etching, introduce lattice damage and defects, causing large leakage current components. Second, inefficient edge termination (ET) designs are incapable of reaching ideal parallel-plane breakdown voltage. This work aims to overcome the aforementioned problems in GaN power devices through innovative designs compatible with a selective-area processing (SAP) technique avoiding both ICP-RIE and ion-implantation. To alleviate the shortcomings in GaN power device ET schemes, novel ET schemes capable of providing ideal parallel-plane breakdown are developed and presented. Also, these designs are fully compliant with the ultra-low-leakage silicon nitride shadowed selective-area growth (SNS-SAG) GaN processing technique. This plasma-assisted molecular-beam epitaxy (PAMBE) based GaN SAP technique is capable of reducing leakage by at least four orders of magnitude compared to ICP-RIE etching. Additionally, mixed-conduction diodes, such as, buried p-base merged p-i-n Schottky (BP-MPS) and buried p-base merged p-i-n junction barrier controlled Schottky (BP-MPJ) diodes capable of reducing leakage current by about five orders of magnitude compared to corresponding p-islet MPS (PI-MPS) diode designs, have been developed. In conjunction with novel ET designs developed in this work and SNS-SAG processing methodology, these high-performance mixed-conduction diodes perfectly fit in the role of snubber diodes in high-speed switching power applications.
Issue Date:2021-04-08
Rights Information:Copyright 2021 Palash Sarker
Date Available in IDEALS:2021-09-17
Date Deposited:2021-05

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