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Title:A Brief Description of the NMP ISA and Benchmarks
Author(s):Wei, Mingliang; Snir, Marc; Torrellas, Josep; Tremaine, R. Brett
Subject(s):computer science
Abstract:The Near Memory Processor (NMP) is a multithreaded vector processor integrated with the memory controller. The NMP works subordinately upon requests from the main processors. The NMP is complementary to the conventional superscalar processors and it is optimized for the bandwidth bounded applications and bit manipulation workloads. A program addressable memory in the NMP, Scratchpad provides an effectively large register set to hold vectors, streams and frequently accessed values. Avoiding saving and restoring the vector registers during context switch, the scratchpad reduces the overhead of the multithreading and enables a simple NMP architectural design. We design an instruction set that includes vector, streaming and bit manipulation instructions. We present the instruction set architecture of the NMP in this report, including register sets, addressing mode and instruction formats. A brief description of the benchmarks is also included.
Issue Date:2005-02
Genre:Technical Report
Type:Text
URI:http://hdl.handle.net/2142/11095
Other Identifier(s):UIUCDCS-R-2005-2633
Rights Information:You are granted permission for the non-commercial reproduction, distribution, display, and performance of this technical report in any format, BUT this permission is only for a period of 45 (forty-five) days from the most recent time that you verified that this technical report is still available from the University of Illinois at Urbana-Champaign Computer Science Department under terms that include this permission. All other rights are reserved by the author(s).
Date Available in IDEALS:2009-04-20


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