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Title:On-chip wireless manycore architectures
Author(s):Franques Garcia, Antonio Maria
Director of Research:Torrellas, Josep
Doctoral Committee Chair(s):Torrellas, Josep
Doctoral Committee Member(s):Misailovic, Sasa; Al-Hassanieh, Haitham; Padua, David; Krishna, Tushar
Department / Program:Computer Science
Discipline:Computer Science
Degree Granting Institution:University of Illinois at Urbana-Champaign
Abstract:Recent computer architecture trends herald the arrival of massive multiprocessors with more than a hundred processor cores within a single package. In this setting, on-chip communication becomes increasingly important, as parallel programs increase the amount of data sharing and signaling between cores. Unfortunately, traditional on-chip networks have been proven to not scale well in terms of latency or energy consumption, slowing down the computation, and jeopardizing the scalability of hundred-core processors. On-chip wireless networks are a novel interconnect paradigm that holds considerable promise for overcoming the communication challenges left unmet by wired networks-on-chip, and for enabling such massive multicore chips. In this thesis, we propose several applications of on-chip wireless technology for manycore architectures, namely: Replica, a manycore that uses wireless communication for synchronization and communication-intensive data; WiDir, which uses on-chip wireless technology to augment a conventional invalidation-based directory cache coherence protocol; and WiChip, a chiplet-based architecture that uses a wireless network to attain scalable communication. Besides the aforementioned applications of on-chip wireless technology, in this thesis we also address some of the challenges that come with the technology. One of the main challenges of on-chip wireless technology is the design of methods that provide fast and efficient access to the wireless channel while adapting to the constant traffic changes within and across applications. Hence, we propose Fuzzy-Token, a simple medium access control protocol that leverages the unique properties of the on-chip scenario to deliver efficient and low-latency access irrespective of the application characteristics.
Issue Date:2021-12-02
Rights Information:Copyright 2021 Antonio Maria Franques Garcia
Date Available in IDEALS:2022-04-29
Date Deposited:2021-12

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