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Title:Techniques for integrated energy-efficient power conversion
Author(s):Pal, Nilanjan
Director of Research:Hanumolu, Pavan Kumar
Doctoral Committee Chair(s):Hanumolu, Pavan Kumar
Doctoral Committee Member(s):Pilawa-Podgurski, Robert; Banerjee, Arijit; Zhou, Jin; Schutt-Aine, Jose
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):DC-DC converters
boost converter, LED-drivers
current sensing
temperature compensation
TDC
delta-sigma ADC
hybrid converter
resistor interpolation
Abstract:Power converters are a fundamental part of any system that seek to transfer electrical energy from one voltage domain to another. Traditionally, the power converter required bulky off-chip power switches to maintain acceptable efficiency which resulted in them occupying a significant portion of the total system volume. As these systems evolved to reduce in volume the corresponding power converters needed to adapt by improving both power density and efficiency. This eventually led to the integration of power switches along with the control circuitry on a single die. This integration presented unique opportunities and challenges from a power converter perspective which has resulted in a renewed focus on integrated power converters. The various DC-DC power converter topologies can be broadly categorised into two classes: switched-inductor and switched-capacitor types. Generally, the switched-inductor type is more suitable for power levels of the order of a few watts or higher, while the switched-capacitor type is more suited to low-power applications of a few hundred milli-watts. Recently, a third category has emerged: hybrid converters which tries to combine the advantages of both the aforementioned categories. The relatively new type of power converter primarily aims to improve power efficiency by easing the trade-off between switching and conduction loss by enabling the use of better power switches. In the first technique, a hybrid boost converter architecture for improving the efficiency of LED drivers used in mobile applications, is presented. By cascading a low-switching frequency time-interleaved series-parallel SC-stage with an inductive boost converter, we facilitate lower voltage-rated switches, thus significantly reducing the switching losses. Charge-sharing losses of the SC stage are minimized by soft-charging flying capacitors with the inductor of the boost stage. Fabricated in 180 nm BCD process, the prototype converter generates 30 V output voltage from a Lithium-ion (Li-ion) battery source. It can provide a load current in the range of 0 to 100 mA with an excellent peak power efficiency of 91.15% at 30 mA, which represents a 3% improvement over the state-of-the-art. In the second technique, a novel current sensing architecture is explored. A new duty-cycle sensing technique with applications in current sensing for DC-DC power converters is presented. A time-based Delta-Sigma ADC with 1-bit delay-DAC accurately measures small changes in the duty-cycle of a PWM waveform. Fabricated in 65 nm general purpose CMOS process, the prototype senses changes in duty-cycle ranging from 4 m up to 20 m with 1% linearity, making it suitable for detecting small load current-dependent changes in the duty-cycle of a regulated DC-DC power converter. The switching clock of a power converter is an important part of the whole system. It is essential to keep the frequency of this clock fixed under various operating conditions in order to prevent the generation of unwanted harmonics which might interfere with the proper functioning of the whole system. For most low-frequency integrated power converters, an on-chip relaxation oscillator is used. Even though this oscillator architecture is very power efficient, it has large variation in frequency over temperature. A method for improving the temperature stability of RC relaxation oscillators by precisely interpolating between resistors with opposing temperature coefficients is presented. By obviating the need for a large trimming network of switches and resistors, it achieves excellent frequency accuracy across PVT. Fabricated in 65 nm CMOS, the prototype 400 kHz oscillator achieves an inaccuracy of 16 ppm/degC (-40degC to 85degC), 2.5 ppm/mV voltage sensitivity, and 5.6 ppm Allan deviation in one second strides.
Issue Date:2021-11-22
Type:Thesis
URI:http://hdl.handle.net/2142/114068
Rights Information:Copyright 2021 Nilanjan Pal
Date Available in IDEALS:2022-04-29
Date Deposited:2021-12


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