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Title:Managing Many-Core Aging
Author(s):Karpuzcu, Rahmet U.
Advisor(s):Torrellas, Josep
Contributor(s):Torrellas, Josep
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):Processor Aging
Voltage Scaling
Process Scaling
Power Wall.
Abstract:Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling. In future designs, the majority of the cores will necessarily have to be dormant at any given time to meet the power budget. To push back the many-core power wall, this work introduces Dynamic Voltage Scaling for Aging Management (DVSAM) — a new scheme for trading off processor aging for performance and power. DVSAM can be used to maximize performance, minimize power, or boost performance for a short life. In addition, this work introduces the BubbleWrap many-core, an architecture that makes use of DVSAM. BubbleWrap identifies the most power-efficient cores on a variation-affected chip and designates them as Throughput cores dedicated to parallel-section execution; the rest of the cores (Expendable cores) are dedicated to sequential sections. In one use of DVSAM, BubbleWrap sacrifices Expendable cores one at a time by running them at elevated V dd for a month or so each, until they completely wear out. Our simulations show that a 32-core BubbleWrap many-core provides substantial improvements over a plain chip. For example, on average, one design runs fully sequential applications at a 22% higher frequency, and fully parallel applications with a 33% higher throughput.
Issue Date:2010-01-06
URI:http://hdl.handle.net/2142/14617
Rights Information:@ 2009 Rahmet Ulya Karpuzcu
Date Available in IDEALS:2010-01-06
Date Deposited:December 2


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