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Title:High-Speed Serial Data Link Design and Simulation
Author(s):Lee, Edward W.
Advisor(s):Schutt-Ainé, José E.
Contributor(s):Schutt-Ainé, José E.
Department / Program:Electrical and Computer Engineering
Discipline:Electrical and Computer Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Serial Link Receiver
Data Recovery
Adaptive Equalization
Decision Feedback Equalizer
Decision Feedback Equalizer (DFE) Receiver
Abstract:This thesis describes the modeling and simulation of 10 Gb/s serial data link architectures. The first architecture uses a continuous-time receiver equalizer to equalize a channel with known frequency response. The second incorporates an adaptive decision feedback equalizer (DFE) for use in unknown or time-varying channels.
Issue Date:2010-01-06
Rights Information:Copyright 2009 Edward W. Lee
Date Available in IDEALS:2012-01-07
Date Deposited:December 2

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