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Title:Modeling and suppression of latchup
Author(s):Farbiz, Farzan
Director of Research:Rosenbaum, Elyse
Doctoral Committee Chair(s):Rosenbaum, Elyse
Doctoral Committee Member(s):Feng, Milton; Schutt-Ainé, José E.; Jou, Shyh-Jye
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Abstract:In this dissertation, an experimental study of latchup is conducted. A semi-physical analytical model is proposed that estimates the latchup susceptibility of a design prior to fabrication. The model can easily be implemented in a circuit simulator and be simulated together with the rest of the design. We will show that depending on the bias conditions and layout geometry, electrons or holes can trigger latchup. Latchup hazards caused by holes and electron injection are studied. The roles of guard rings are investigated. The impacts of N-type and P-type guard rings are reported. The guard-ring efficacy under high-level injection conditions and short injection pulse durations are also reported. We show that N-well guard rings in particular become less efficient as the amount of injection increases or when the injection-pulse duration is shortened. The effects of guard rings are incorporated into the model. We demonstrate that whether electron injection or hole injection is the worst case, that is, has the lowest latchup susceptibility, depends on the pulse-width of the injection current. Electron injection is the worst case condition during static latchup testing, i.e., when the injection pulse-width is long. This condition is generally used for product qualification. However, real world stresses, such as cable discharges, are transient, in which case hole injection is the worst case condition. Chapters 1 and 2 give background on latchup. They explain the difference between internal and external latchup and show that latchup can be triggered by static or transient events. A brief history of previous work on latchup is presented. Chapter 3 focuses on internal latchup. Latchup triggering modes and characterization methods are explained. Chapter 4 is devoted to analysis of external latchup and the standard latchup tests. The term collection efficiency is defined in this chapter to represent the number of injected carriers participating in triggering latchup. Circuit-level models are proposed to understand latchup behavior under various testing conditions. These circuit schematics provide a base for modeling latchup susceptibility later in Chapter 6. Measurement results of the collection efficiency and external latchup trigger current are presented and investigated in Chapter 5. The effects of layout geometry are studied. Guard ring interactions and their effect on latchup resilience are explained. A model for the external latchup trigger current is proposed and compared to the measurement results in Chapter 6. The model can be used in a circuit simulator to estimate the latchup susceptibility of a layout. The model captures the effects of the guard rings. Transient latchup testing is discussed in Chapter 7. The worst-case testing conditions for static and transient latchup are reported. Guard rings are evaluated under transient latchup testing. Finally, conclusions are drawn and future work is suggested in Chapter 8.
Issue Date:2010-05-19
Rights Information:Copyright 2010 Farzan Farbiz
Date Available in IDEALS:2010-05-19
Date Deposited:May 2010

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