Switching density analysis for power and reliability in VLSI circuits

Abstract

Advances in integrated circuit fabrication and improved computer-aided-design tools have made it possible to design and fabricate multi-million transistor integrated circuits. With such a large number of devices in a single package, new design and analysis issues have emerged. The power consumption of these giga-scale integrated circuits becomes a serious concern for packaging, heat dissipation, and energy efficiency reasons. Reliability of such complex circuits also is a serious design concern since failure of a single transistor may induce functional failure of the entire circuit. In this thesis, four key issues relating to these problems are considered.

First, short-circuit power consumption is considered. We present a probabilistic algorithm for the analysis of short-circuit power in VLSI designs. This technique is used to assess the significance of short-circuit power consumption during power optimization. We also analyze short-circuit power in static CMOS gates, D flip-flops, multiplexors, and tri-state I/O pads.

Second, we consider the issue of guaranteeing the final accuracy of a simulation-based switching density estimate. We propose a set of stopping criteria for a specified final accuracy. Additionally, algorithms to estimate the number of required input patterns are proposed.

Third, we address the issue of estimating maximum current and power consumption through simulation. Order statistics are used to provide statistically improved estimates for these maxima. Results are presented which provide confidence intervals on the estimated maximum values and bound typical values for both current and power.

Finally, worst-case switching density is considered. Algorithms based on the concept of single-transition intervals (STIs) are presented which can bound the maximum switching density, and extensions based on gate functionality are proposed.