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Title:Simulation of faults causing analog behavior in digital circuits
Author(s):Yang, Fred Lei
Doctoral Committee Chair(s):Saleh, Resve A.
Department / Program:Electrical and Computer Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Engineering, Electronics and Electrical
Abstract:The purpose of this research is to develop effective simulation methods for electrically oriented faults in digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. In particular, we are interested in the simulation of permanent electrical faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level analysis due to their electrical nature. These problems are addressed using mixed-mode simulation techniques in which the fault-free portions of the circuit are simulated using logic-level simulation techniques while the faulty portions of the circuit are simulated using electrical-level simulation techniques. In addition, since transient faults manifest their electrical nature only for a very short period of time, a dynamic mixed-mode simulation technique is developed to take advantage of this property to speed up further the simulation of transient faults. These algorithms have been implemented in the programs F/SPLICE3 and DYNAMO with significant improvements in simulation speed compared to those for previous approaches.
Issue Date:1992
Type:Text
Language:English
URI:http://hdl.handle.net/2142/19306
Rights Information:Copyright 1992 Yang, Fred Lei
Date Available in IDEALS:2011-05-07
Identifier in Online Catalog:AAI9305740
OCLC Identifier:(UMI)AAI9305740


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