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Title:Hardware and software for functional and fine-grain parallelism
Author(s):Beckmann, Carl Josef
Doctoral Committee Chair(s):Polychronopoulos, Constantine D.
Department / Program:Electrical and Computer Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Computer Science
Abstract:This thesis examines nonloop parallelism at both fine and coarse levels of granularity in numerical FORTRAN programs. Measurements of the extent of this functional parallelism in a number of FORTRAN codes are presented, as well as compiler and run-time algorithms designed to exploit it. Hardware and software embodiments of the dynamic scheduling algorithms are developed, along with the compiler optimizations necessary to make these practical.
The impact of fine grain functional parallelism on instruction-level architecture is explored, and it is shown that dynamic instruction scheduling hardware based on the functional parallelism scheduling algorithms can yield a significant improvement over static scheduling on conventional RISC processors when the latency of memory accesses is highly variable. Measurements of the characteristics of a set of FORTRAN benchmark programs indicates that such a hardware realization is feasible in practice.
Issue Date:1993
Rights Information:Copyright 1993 Beckmann, Carl Josef
Date Available in IDEALS:2011-05-07
Identifier in Online Catalog:AAI9411565
OCLC Identifier:(UMI)AAI9411565

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