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|Title:||Parallel processing for VLSI simulation|
|Author(s):||Mueller-Thuns, Robert Bernard|
|Doctoral Committee Chair(s):||Jones, Lawrence|
|Department / Program:||Computer Science|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Abstract:||Simulation has become indispensable in the process of designing, verifying, and testing complex digital systems because it is flexible and cost-effective. As the complexity of the designs grows the time and memory requirements of simulation increase and simulation can become a bottleneck. At the same time, parallel and distributed processing is becoming available and offers the potential of economical high performance computing. However, software and applications are lagging behind at this stage.
The research reported in this thesis is motivated by both the increased need for simulation and the emergence of general purpose parallel computers. After reviewing previous work in the area of parallel simulation, we relate the issues of portability and scalability to our application and define a high-level process model view for parallel simulation. In the following, we report the results of two application studies. We first address parallel gate-level logic and fault simulation and then investigate parallel switch-level simulation; for both we introduce partitioning and simulation algorithms and present extensive performance evaluations. Directions for future research and an outlook for the future of parallel simulation conclude the thesis.
|Rights Information:||Copyright 1990 Mueller-Thuns, Robert Bernard|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9114355|