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Title: | Design, analysis and reconfiguration of defect-tolerant VLSI and parallel processor arrays |
Author(s): | Shi, Weiping |
Doctoral Committee Chair(s): | Fuchs, W. Kent |
Department / Program: | Computer Science |
Discipline: | Computer Science |
Degree Granting Institution: | University of Illinois at Urbana-Champaign |
Degree: | Ph.D. |
Genre: | Dissertation |
Subject(s): | Engineering, Electronics and Electrical
Computer Science |
Abstract: | In this thesis, several design, analysis and reconfiguration problems in defect-tolerant VLSI and parallel processor arrays are studied. The NP-hard memory array reconfiguration problem is formulated as a random graph problem, and a provably average-case polynomial time algorithm is presented, while all previous memory reconfiguration algorithms were given without an average-case time complexity analysis. The implemented algorithm runs faster than existing heuristics when the problem size is large. For reconfigurable pipelines, an analytical estimation of the yield is given, while all previous yield estimations were through experiments. A large area defect-tolerant tree architecture is designed that has 99% harvest rate, while all previous designs have harvest rate that is asymptotically 0%. Finally, a general framework for computing the optimal spare allocation is developed for many VLSI redundant systems. |
Issue Date: | 1992 |
Type: | Text |
Language: | English |
URI: | http://hdl.handle.net/2142/19803 |
Rights Information: | Copyright 1992 Shi, Weiping |
Date Available in IDEALS: | 2011-05-07 |
Identifier in Online Catalog: | AAI9305693 |
OCLC Identifier: | (UMI)AAI9305693 |
This item appears in the following Collection(s)
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Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois -
Dissertations and Theses - Computer Science
Dissertations and Theses from the Dept. of Computer Science