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|Title:||Computationally efficient methods for accurate timing and reliability simulation of ultralarge MOS circuits|
|Doctoral Committee Chair(s):||Liu, C.L.|
|Department / Program:||Computer Science|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical
|Abstract:||A new approach to MOS circuit fast timing simulation is shown in this thesis. A generic MOS circuit primitive is shown along with the exact analytic solution of its state equation, a nonlinear Ricatti equation.
A fast timing digital CMOS circuit simulator ILLIADS has been developed using the generic circuit primitive as well as its exact analytic solution. ILLIADS has been shown to be superior to other fast MOS timing simulators tested in both accuracy and speed. A modified waveform relaxation method for handling circuits with feedbacks is also presented in this thesis. A new algorithm taking advantages of event-driven technique and waveform relaxation method has been developed and applied. With this algorithm, simulation of a collection of ISCAS89 benchmark circuits reveals that the speedup of ILLIADS over SPICE is roughly 3N, where N is the number of transistors in a circuit. To incorporate the channel length modulation effect, an accurate and efficient method has also been developed. With this method, channel length modulation is handled with only a 10% speedup penalty. ILLIADS has been able to simulate a combinational circuit consisting of 235,000 transistors for one cycle output in 10.5 minutes real time in a workstation environment.
Also presented in the thesis is a new first-time approach to fast circuit reliability simulation using a simple damaged transistor model. The new approach has made possible accurate and fast reliability simulation of large MOS circuits.
|Rights Information:||Copyright 1991 Shih, Yung-Ho|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9210989|