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Worst case voltage drops in power and ground buses of CMOS VLSI circuits

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Title: Worst case voltage drops in power and ground buses of CMOS VLSI circuits
Author(s): Kriplani, Harish
Doctoral Committee Chair(s): Hajj, Ibrahim N.
Department / Program: Electrical and Computer Engineering
Discipline: Electrical Engineering
Degree Granting Institution: University of Illinois at Urbana-Champaign
Degree: Ph.D.
Genre: Dissertation
Subject(s): Engineering, Electronics and Electrical Computer Science
Abstract: Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the P&G buses to study the severity of the voltage drop problems and to redesign the supply buses accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this thesis, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result from the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits.
Issue Date: 1994
Type: Text
Language: English
URI: http://hdl.handle.net/2142/20706
Rights Information: Copyright 1994 Kriplani, Harish
Date Available in IDEALS: 2011-05-07
Identifier in Online Catalog: AAI9416387
OCLC Identifier: (UMI)AAI9416387
 

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