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|Title:||Use of architectural-level primitives in system-level diagnosis and speed up of test vector generation|
|Author(s):||Kunda, Ramachandra P.|
|Doctoral Committee Chair(s):||Patel, Janak H.|
|Department / Program:||Electrical and Computer Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical|
|Abstract:||Test generation is an important part of a circuit as the test vectors are used during the design, manufacture, system integration, and throughout the life-cycle of the circuit in order to detect the presence of defects. The very large scale integration (VLSI) test generation problem has been one of the most complex and time-consuming problems. This is a major bottleneck in the design cycle of the circuit. The problem is further complicated by rapid advances in VLSI technology, such as in CMOS, where the traditional stuck-at fault model is inadequate, and the increase in gate to pin ratio makes it difficult to access and observe the internal signals.
In this thesis, we present two different approaches to attack this problem. The first approach is concerned mainly with the generation of functional-level tests that are used during system debug and integration. A functional diagnostic methodology as well as techniques to diagnose various blocks of a multiprocessor system are presented. The approach has been used successfully to debug and integrate a prototype multiprocessor system.
In the second approach, we present a hierarchical and high-level model which uses architectural-level primitives for fault propagation and signal value justification to speed up the automatic test vector generation process. We present methods for fault propagation and value justification through the architectural-level primitives. In order to reduce the number of backtracks, the algorithm employs the strategy of dependency-directed backtracking, which attempts to resolve the conflicts by changing the signal values causing the conflict. Experimental results using this approach for test vector generation are presented.
|Rights Information:||Copyright 1990 Kunda, Ramachandra P.|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9114304|
This item appears in the following Collection(s)
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering