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|Title:||Functional models for MOS VLSI circuits|
|Author(s):||Wehbeh, Jalal Anis|
|Doctoral Committee Chair(s):||Saab, Daniel G.|
|Department / Program:||Electrical and Computer Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical|
|Abstract:||In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design applications for VLSI circuits is considered. A method for the automatic generation of functional models for switch- and gate-level circuits is presented. In addition, the use of these models is considered in four CAD applications: switch-level simulation, verification of transistor-level circuits, the initializability of synchronous sequential circuits, and Boolean matching.
For switch-level simulation, extracted models are used to speed up the simulation process in a hierarchical simulation environment. When extracted models are used to represent modules at different levels in the hierarchy a considerable amount of speedup can be achieved. This speedup can vary from about three times, when dc-connected components are represented by their functional models, to around nine or ten times, when models are used to represent modules at higher levels in the hierarchy.
For verification of transistor-level circuits, the model extraction routines are modified to generate a finite state machine description of the circuit. This description is then verified against another finite state machine description of the design based on formal methods for the verification of sequential circuits.
A new method for determining the initializability of a sequential circuit and for generating its initialization sequence is also presented. This method is based on the structural decomposition of the state subspace and can handle both logical (using X-value simulation) and functional initializabilities. In addition, the effect of using initialization sequences as pre-test sequences during automatic-test-pattern-generation (ATPG) is examined. Improved fault coverage is achieved, when the good and faulty circuits are initialized, by use of initialization sequences, prior to the generation of test vectors.
Finally, the use of extracted functional models for Boolean matching during technology mapping in a logic synthesis environment is considered. A method for generating signatures, to be used to reduce the number of possible library elements that match a given module in the circuit, is developed. The signature generated is also used for determining the input correspondence and for finding symmetric inputs. Results for generating these signatures for some typical circuits are also presented.
|Rights Information:||Copyright 1994 Wehbeh, Jalal Anis|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9512591|
This item appears in the following Collection(s)
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering