Files in this item



application/pdf9305627.pdf (6MB)Restricted to U of Illinois
(no description provided)PDF


Title:Preparation and characterization of in situ deposited metal-insulator-III-V semiconductor devices
Author(s):Mui, David Sai Lai
Doctoral Committee Chair(s):Morkoc, Hadis
Department / Program:Electrical and Computer Engineering
Discipline:Electrical Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Engineering, Electronics and Electrical
Abstract:In this thesis, the growth, fabrication, and characterization of in-situ deposited III-V semiconductor-based Metal-Insulator-Semiconductor (MIS) devices are described. The two III-V semiconductors investigated were $\rm In\sb{0.53}Ga\sb{0.47}As$ and GaAs. The problems related to air exposure of the semiconductor surface in ex-situ process was circumvented in this work by depositing the insulator in-situ. A special growth system which integrates several MBE growth chambers with an ultrahigh vacuum chemical vapor deposition chamber was designed and built. All of the chambers in this growth system are connected by vacuum transfer tubes and sample transfer takes place under ultrahigh vacuum conditions. The technique of electron cyclotron resonance plasma-assisted deposition was used for the deposition of $\rm Si\sb3N\sb4$ and Si.
By using a spatially extended interface, the role of tunneling-related trapping in accumulation bias was discussed. It was shown that the circuit model on which the conventional SiO$\sb2/$Si interface characterization techniques were based was not applicable when tunneling-related trapping occurred. A new circuit model appropriate for tunneling-related trapping was derived. Measured frequency dispersion on ICS interfaces was shown to be adequately explained by the new circuit model. With the new circuit model, the interface trap density near the conduction band edge and the effective thickness of the interface were deduced.
In order to utilize these start-of-the-art interfaces in MISFETs, a self-aligned gate process was developed. The gaps between the gate/drain and gate/source metallizations obtained from this self-aligned technique were of the order of 1000-2000 A. Extrinsic transconductances of close to 240 mS/mm of 2.2 $\mu$m gate $\rm In\sb{0.53}Ga\sb{0.47}As$ depletion mode MIS Field-Effect Transistors were obtained.
Issue Date:1992
Rights Information:Copyright 1992 Mui, David Sai Lai
Date Available in IDEALS:2011-05-07
Identifier in Online Catalog:AAI9305627
OCLC Identifier:(UMI)AAI9305627

This item appears in the following Collection(s)

Item Statistics