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|Title:||Parallel algorithms for standard cell placement using simulated annealing|
|Author(s):||Chandy, John A.|
|Doctoral Committee Chair(s):||Banerjee, Prithviraj|
|Department / Program:||Electrical and Computer Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical
|Abstract:||As modern VLSI designs have become larger and more complicated, the computational requirements for design automation tools have also increased. As a result, the parallelization of these tools is of great importance. One of the more computationally intensive parts of the entire VLSI design process is the placement process. Simulated-annealing-based approaches have been the most popular and effective methods for cell placement. In this thesis, parallelization approaches to simulated-annealing-based standard cell placement are presented.
In this work, four parallel algorithms have been investigated, with two that provide scalable behavior as well as acceptable quality. The first is the parallel moves approach based on work by Kim (1,2). The second algorithm is a multiple Markov chains approach that gives nearly linear speedups with very little loss of quality. This approach is suitable for small scale multiprocessors and for circuits that are small enough to fit in the memory of a single node. The next algorithm is known as speculative computation and is not as effective. The final algorithm addresses the memory scalability problems by partitioning the circuit across the nodes. This circuit-partitioned approach provides speedups to larger numbers of processors with little loss of quality. All of the algorithms have been implemented using the ProperCAD II environment (3), and the circuit-partitioned work has also been implemented using the Message Passing Interface (MPI) (4).
The placement algorithms discussed above dealt only with minimization of the wirelength and indirectly area minimization. For current high density circuits, this approach is no longer appropriate, and more performance driven techniques are needed. We have, therefore, also developed a new algorithm for sequential timing driven cell placement. Because the addition of timing driven features to standard cell placement adds significant overhead to the computation, time, we have also developed an algorithm for its parallelization.
|Rights Information:||Copyright 1996 Chandy, John Attupurathu|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9712216|
This item appears in the following Collection(s)
Dissertations and Theses - Computer Science
Dissertations and Theses from the Dept. of Computer Science
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering