Timing verification and synthesis of circuits for delay fault testability

Abstract

This thesis concerns the problem of timing verification and synthesis of circuits for robust delay fault testability. The timing verification algorithm uses Register Transfer Level (RTL) descriptions to eliminate false paths (non-sensitizable) due to redundancy, reconvergent fanout, and control signal constraints. The RTL descriptions help to prune the search space because only valid paths are considered.

The critical paths obtained from the timing verifier have to be tested for any delay faults. To make the robust delay test generation easier, multilevel combinational logic circuits are synthesized for delay fault testability. Given a multilevel description of a combinational logic circuit, blocked or dependent paths may be present. Blocked or dependent paths due to reconvergent fanout can destroy robustness of tests. A set of path segments called essential paths is checked for blockage or dependency, and a local transformation enhances the delay fault testability of the circuit. It has been shown that a robust delay test can be obtained as a by-product of the logic synthesis procedure.