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|Title:||Synthesis techniques for VLSI low-power circuits|
|Author(s):||Panda, Rajendran Venkatachari|
|Doctoral Committee Chair(s):||Najm, Farid|
|Department / Program:||Computer Science|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical|
|Abstract:||This thesis presents techniques for automatically synthesizing VLSI circuits having low power dissipation. Power consumption of static CMOS and BiCMOS circuits is almost entirely dependent on the extent of switching activity at the circuit nodes and the capacitances switched. We describe algorithms to restructure a circuit so that the switching and capacitances are optimized.
The switching itself is dependent on the Boolean functions, thus making logic design a viable stage for power optimization. Besides, a number of other factors, viz. the loads switched, the delay characteristics of gates, the arrival times, and switching patterns of the signals, also determine the dynamic power. The proposed method considers all these factors simultaneously to guide an optimization process.
Restructuring is proposed at two stages: (i) the technology decomposition stage and (ii) a post-mapping stage. At the former stage, nodes are decomposed into binary trees of minimum total switching activity. With such decompositions, it is shown experimentally that, the subsequent mapping step produces a network that has very low power consumption. In the post-mapping phase, circuit transformations in the nature of transduction procedures are applied to manipulate the Boolean functions at the nodes for reduced switching, to shift loads from higher activity nodes to lower activity nodes, and to curtail generation and propagation of spurious transitions. These transformations are applied in an iterative manner, exploring the design space over the Boolean don't cares, using the concept of Permissible Boolean Functions.
The algorithms have been implemented as the core of a combinational logic synthesis system for power optimization, called LogicPower. Their application on a variety of benchmark circuits has shown significant power reduction, at minimal or no cost of the area or delay of these circuits. The proposed ideas are also applicable to semi-custom and full-custom designs.
|Rights Information:||Copyright 1996 Rajendran Venkatachari Panda|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9712392|