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|Title:||Modeling simulation and design guidelines for EOS/ESD protection circuits in CMOS technologies|
|Doctoral Committee Chair(s):||Kang, Sung Mo|
|Department / Program:||Electrical and Computer Engineering|
|Degree Granting Institution:||University of Illinois at Urbana-Champaign|
|Subject(s):||Engineering, Electronics and Electrical
Physics, Electricity and Magnetism
Physics, Condensed Matter
|Abstract:||Electrical Overstress (EOS) and Electrostatic Discharge (ESD) are major causes for integrated circuit (IC) field failures. Industry surveys indicate that nearly 50% of all IC field failures can be attributed to EOS/ESD events. The susceptibility to EOS/ESD increases as the minimum feature size in ICs is reduced. In order to protect the internal circuitry from EOS/ESD, various on-chip protection schemes have been proposed and are being used in commercial ICs.
In this thesis, we have provided a review of various on-chip protection circuits commonly used in advanced CMOS ICs. We propose that current profiles should be used for EOS qualification. We show that current profiles, along with failure analyses, can be used to develop useful design guidelines for EOS/ESD protection circuit layout. We investigate the effect of chip capacitance on the EOS/ESD performance of protection circuits and provide guidelines for device design. Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications. We provide practical guidelines for designing protection devices in this technology.
Recent advances in processing technology and very-large-scale integration (VLSI) scaling has increased the demand for more effective protection circuits. So far, no significant modeling programs were available to analyze and design these circuits. We have developed models which describe the high current behavior in MOSFETs, diffusion resistors, reverse-biased diodes and bipolar transistors. These models have been included in the circuit-level electrothermal simulator, iETSIM.
It has been shown that at second breakdown, the protection device suffers permanent damage. By modeling the device behavior up to the onset of second breakdown, we can determine the operation limit of the protection element. We have developed electrothermal models to describe the onset of second breakdown in the protection devices. In semiconductor junctions that are reverse-biased by an EOS event, second breakdown is shown to occur when the thermal generation current becomes high enough to sustain the stress and the generation of carriers due to impact ionization decreases. Electrothermal models for MOSFETs, diffusion resistors, diodes and bipolar transistors have been included in iETSIM, which can predict the EOS robustness of these protection elements.
|Rights Information:||Copyright 1996 Ramaswamy, Sridhar|
|Date Available in IDEALS:||2011-05-07|
|Identifier in Online Catalog:||AAI9712413|
This item appears in the following Collection(s)
Graduate Dissertations and Theses at Illinois
Graduate Theses and Dissertations at Illinois
Dissertations and Theses - Electrical and Computer Engineering
Dissertations and Theses in Electrical and Computer Engineering